Dual floating gate programmable read only memory cell structure and method for its fabrication and operation

ABSTRACT

A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while source and drain regions are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. Methods of fabricating the memory cell and operating it are also disclosed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a unique cell structure for anon-volatile memory used in erasable programmable, read only memorydevices such as EEPROM and flash memory. More particularly the inventionrelates to a cell structure having a transistor which employs a pair offloating gates to store multi-bit binary data and to methods forfabricating and operating the memory cell.

[0003] 2. Discussion of the Related Art

[0004] Nonvolatile memory cells are known in which multiple bits of datacan be stored by placing various levels of charge on the floating gateof the cell transistor which in turn affects the transistor thresholdvoltage Vt. By storing differing levels of charge and thus obtainingdifferent levels of threshold voltage Vt a cell can store more than onebit of information therein. For example, in order to store two binarybits four levels of charge and correspondingly levels of Vt may be used.During a read operation, a decoder senses the transistor threshold Vt todetermine the corresponding binary value of the multi-bit information,e.g. 00, 01, 10, 11.

[0005] In order to store higher densities of binary bits in the cell, itis necessary to correspondingly increase the number of Vt voltage levelscorresponding to the number of bits of information which are stored. Forexample, in order to store three bits, eight levels of charge must bestored. As higher voltages are used, for charge storage, it introducesproblems in the memory array including requiring a higher operatingvoltage, more power dissipation, and complex circuitry for reading,erasing and decoding the binary information. Moreover, if the number ofcharge levels increases without increasing the supply voltage, itbecomes more difficult to detect the correct stored charge level.Accordingly, it becomes progressively more difficult to store largernumbers of digits of information in an erasable programmable memory cellhaving a floating gate.

SUMMARY OF THE INVENTION

[0006] The present invention is designed to alleviate some of theproblems associated with the storage of multi-bit binary information inthe memory cell of an erasable programmable read only memory array. Thepresent invention provides two separate floating gates for eachtransistor within the memory cell. The control gate of the transistor isconnected to a word line provided over both floating gates while each ofthe source and drain regions of the transistor are connected torespective digit lines. By appropriately controlling the voltagedifferential applied to the word line and digit lines and timing ofapplication of the voltage differential, separate charges can be storedand read from each of the two floating gates of the transistor. Byutilizing two separate floating gates to respectively store chargeswithin the transistor, the reading, writing, erasing and decoding of themulti-bit information can be done with lower voltages and powerdissipation than would otherwise be required for a single floating gatetransistor and the decoding of many levels of stored charges is notrequired. Therefore, repeated storage of multi-bit data does not degradethe cell as much as occurs with a single floating gate transistor cell.

[0007] Thus, the memory cell of the invention can be used to store twoor more bits of information by separately controlling the charges storedin each of the floating gates.

[0008] The invention also relates to fabrication methods for the dualfloating gate transistor as well as to a method for operating thetransistor to write and read multi-bit digital data to and from thememory cell.

[0009] It should be understood that the memory cell of the invention canbe used in EEPROM flash memory arrays, and other erasable programmableread only memory arrays. For purposes of simplified discussion, thisspecification will discuss the invention in the context of a flashmemory array; however, it should be understood that the memory cell ofthe invention can be used in any read only memory array which iselectronically erasable and reprogrammable.

[0010] The foregoing and other advantages and features of the inventionwill be more readily appreciated from the following detailed descriptionof the invention which is provided in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 illustrates the electrical schematic of a memory cellconstructed in accordance with the invention;

[0012]FIG. 2 illustrates an electrical schematic of an array of memorycells arranged in accordance with the invention;

[0013]FIG. 3 illustrates a top view of the topology of the memory cellconstructed in accordance with the invention;

[0014]FIGS. 4A and 4B represent timing diagrams for activating the digitlines and row line to write binary data “01” or “10” into a memory cell;

[0015]FIGS. 5A, 5B, and 5C illustrate the timing diagrams for activatingthe digit lines and row line to write binary data “11” into the memorycell;

[0016]FIGS. 6A, 6B and 6C illustrate timing diagrams for activating thedigit lines and row line to read a stored multi-bit binary value fromthe memory cell;

[0017]FIGS. 7 through 18 illustrate the steps for constructing a memorycell in accordance with a first fabrication embodiment of the invention;

[0018]FIGS. 19 through 24 illustrate the steps for constructing a memorycell in accordance with a second fabrication embodiment of theinvention;

[0019]FIG. 25 illustrates use of the invention in a computer system;and,

[0020]FIG. 26 illustrates another technique for activating the digitlines and row line to read a stored multi-bit binary value from thememory cell.

DETAILED DESCRIPTION OF THE INVENTION

[0021]FIG. 1 illustrates a memory cell constructed in accordance withthe teachings of the invention. The memory cell is formed of a MOSFETtransistor 1 having respective source and drain regions 8 and 10, a pairof floating gates 3 and 5, and a control gate 7 provided over bothfloating gates 3 and 5. The source 8 is respectively connected to afirst digit line 25, and the drain 10 is respectively connected to asecond digit line 27. The control gate 7 is connected to a row (word)line 19.

[0022] The manner in which the transistor shown in FIG. 1 is integratedinto a memory array is illustrated in FIGS. 2 and 3, where FIG. 2illustrates the electrical connection of the FIG. 1 transistor into amemory array and FIG. 3 illustrates in schematic form a top view ofportion of a silicon substrate containing a portion of the memory array.

[0023]FIG. 3 shows a memory cell 17 which contains the transistor 1structure shown in FIG. 1. Row line 19 extends over respective floatinggate regions 3 and 5. Digit lines 25 and 27, which are perpendicular torow line 19, are also illustrated as respectively extending over, andconnecting with, source and drain regions 8 and 10. Each transistor isthus controlled by voltages applied to the row line 19 which covers bothfloating gates 3 and 5 and the respective digit lines 25 and 27electrically connected to source and drain regions 8 and 10.

[0024] It should be noted that although the above description referencesregion 8 as a source and region 10 as a drain, in fact, during theprogramming and readout operations, transistor 1 is operated so thateach of regions 8 and 10 operate at one time or another as a source or adrain. Accordingly, for purposes of further discussion it should berecognized that whenever a region is identified as source or a drainregion, it is only for convenience and that in fact during operation ofthe transistor either region 8 or 10 could be a source or a draindepending on the manner in which the transistor is being controlled byvoltages applied to the row line 19 and digit line 25 and 27 conductors.

[0025]FIG. 3 further illustrates in block diagram format a circuit 11labeled row decode and read, write, erase (RWE) functions. Circuit 11forms part of an electric circuit which supplies the necessary voltagecontrol signals to the row conductor 19 during execution of a read,write or erase operation. The row conductor 19 cooperates with digitlines 25 and 27, which are in turn activated by a digit line driver andsense amplifiers circuit 13 which is also part of an electric circuitfor supplying the necessary voltage control signals to the digit lines25, 27 during execution of a read, write or erase operation. Circuit 13is connected to a timing block 33 which is run off a dock 25, as shownin FIG. 2.

[0026] The electrical schematic connection of a memory array using theFIG. 1 memory cell is illustrated in greater detail in FIG. 2 whichshows a portion of a memory array. There, each transistor in the arrayis shown in greater detail as is the connection to the row decoder andRWE circuit 11, the timing block 33, the dock 35 the odd (O) and even(E) digit lines 25, 27 and the digitline drivers and sense amplifierscircuit 13. Circuit 13 is in turn connected to a multi-bit decodercircuit 37. The function of decoder 37 is to decode the voltages whichare sensed by the sense amplifiers on the odd and even digit lines 25and 27 when a particular memory cell is read to thereby decode the valueof the multi-bit information stored within the memory cell. The decodedmulti-bit binary value, e.g. 00, 01, 10, 11 for a two-bit cell, issupplied out of the decoder block 37 as read data 45. The multi-bitdecoder circuit 37 is also connected to a digit line decoder circuit 39which decodes digit line addresses 42 for reading and writinginformation from and to a particular memory cell transistor 1. Digitline decoder circuit 39 also has a data input 41 which is used toprogram data into the memory cell transistor 1 as will be described indetail below. The row decoder also contains a row address input 47 aswell as an RWE input from a programming state device 49 i.e. a memorycontroller, which determines which of the read, write and erase memoryoperations is to be performed so that both the row decoder and RWEcircuit 11 and digitline drivers and sense amplifiers circuit 13 areappropriately operated to execute either a read, write or eraseoperation. The row decoder and RWE function circuit 11 is shown asconnected to row lines 19 through respective driver amplifiers 67.

[0027] As noted earlier, the present invention utilizes a pair offloating gates 3 and 5 in each memory cell transistor to store chargesrepresenting the multi-bit binary data which is stored in each memorycell. For ease of subsequent discussion, we will assume for the momentthat two binary bits of information are to be stored in each memorycell, i.e., one of the four states 00, 01, 10, and 11. In the followingdiscussion, all the voltages and timing signals similar to the voltagesand timing signals typically used in operation of a single floating gatetransistor. Thus, the dual floating gate cell of the invention is ableto easily store multi-bit binary data in a cell which operates in amanner which is similar to a conventional flash memory cell.

[0028] The programming of a memory cell to write a 01 or 10 state isillustrated in FIGS. 4A and 4B. The signal relationship is shown whenFIGS. 4A and 4b are considered together. FIG. 4A represents the timingof a voltage which is applied to one of the digit lines (odd or even) bythe digitline drivers and sense amplifiers circuit 13 depending onwhether the incoming data 41 is to be stored as a 01 or 10 condition. Asshown in FIG. 4A, a pulse having a duration in the range of 2 to 10microseconds, and preferably of approximately 4 microseconds (us)duration, and at a level of approximately 5 volts, is applied to digitline (again either odd or even depending on whether the programmedcondition is 01 or 10) while at the same time, row line 19 has a pulseapplied thereto of approximately 10 volts for a period in the range of20-100 microseconds and preferably of approximately 60 microseconds(us). As shown in FIGS. 4A and 4B, the row voltage is applied first,followed by the digit line voltage approximately 60 nanoseconds (ns)later. The overlapping voltages applied to the row line and digit line,creates a voltage differential across a floating gate to which the digitline corresponds causing the floating gate to store a charge.

[0029]FIGS. 5A, 5B and 5C, illustrate the timing diagrams for writing a11 state into a memory cell transistor 1. As shown in FIG. 5A, the evendigit line e.g. digit line 27, has a pulse in the range of 2 to 10microseconds and preferably of approximate 3 microseconds (us) appliedthereto, while at the same time the row line, has approximately 10 voltsapplied thereto. The digit line 27 pulse occurs after the beginning ofthe row line pulse. This charges the floating gate associated with evendigit line 27. After the digit line 27 is deactivated for approximately60 ns, then the odd digit line 25 is activated for 2 to 10 microsecondsand preferably for approximately 5 microseconds (us). During this periodthe row line 19 remains active throughout a period in the range of 20 to100 microseconds and preferably for approximately, 60 microseconds (us).In this manner, both digit lines are activated in sequence while the rowline is activated to cause the differential voltage between the row lineand each-digit line to store a charge in each of the floating gateregions 3 and 5.

[0030] The manner in which stored charges can be read out from thetransistor 1 is illustrated in FIGS. 6A, 6B and 6C. During a readoperation, each of the digit lines is again activated, but this time, ata much lower voltage. As shown in FIGS. 6A and 6B, the digit lines haveapproximately 0.8 volt applied thereto. Again, this voltage is appliedin sequence so that first the even digit line 27 has the voltage appliedfor a period in the range of 2 to milliseconds (ms) and preferably forapproximately 3.5 milliseconds, following which, the odd digit line 25has the same voltage applied a period in the range of 2 to

[0031]10 milliseconds and preferably for approximately 3.5 milliseconds,so that in total, approximately 7 milliseconds are required for a readoperation. During the entire time that the even and odd digit lines 27and 25 are sequentially activated, the row line is activated with ahigher voltage of approximately 5 volts for a period in the range of20-100 milliseconds and for preferably approximately 60 millisecondscreating a differential voltage across the corresponding floating gates.This differential voltage between the row line 19 and each of therespective digit lines 25, 27 causes a read out through the senseamplifiers within the digitline drivers and sense amplifiers circuit 13(FIG. 2) of a voltage value corresponding to the respective chargesstored in each of the two floating gates 3 and 5 for each transistor 1.The output voltages from the respective even and odd digit lines areapplied to the decoder 37 illustrated in FIG. 2, from the senseamplifiers. Decoder 37 takes the two voltages from the odd and evendigit lines (25 and 27) and determines which of the states 00, 01, 10,or 11 was previously stored in the transistor 1. This data is thenoutput via bus 45 from the decoder 37.

[0032] Each memory cell which is selected for either a write or read ofdata is addressed by the row decoder 11 and digit line decoder 39 in aconventional fashion. Accordingly, a detailed discussion of how row anddigit address decoders operate will not be provided herein. Suffice itto say that when a digit line is addressed there are two digit lines(odd and even) which are activated in sequence for a read operation andfor writing the 11 state, while one or the other of the digit lines isactivated for writing a 01 or 10 value into the memory cell.

[0033] Data is erased from transistor 1 by applying differentialvoltages across the row and digit lines in a manner which causes thecharges stored within the floating gates to either tunnel to thedigitlines, or tunnel to the substrate. This restores the cell to a 00state. In the case of the former, a voltage differential is applied bysetting the row voltage to approximately zero volts while the digitlines are set at approximately 10 volts. By doing this, the electronswhich are stored at the floating gate are attracted and tunnel to thedigit line positive potential. Also, during the erase cycle, the digitlines alternate so that first the even 27 and then the odd 25 (orvice-versa) digit lines have the approximately 10 volts applied to them,while the row conductor remains at approximately zero volts. It is alsopossible to set the digit lines at a lower voltage, for example, 6volts, while the word line has approximately 4 volts applied to it. Thedifferential voltage across the floating gate regions is stillapproximately 10 volts as before and erasure of the floating gate regioncharges will occur.

[0034] An alternative way to erase the memory cells is to have theelectrons tunnel to the substrate from the two floating gates 3, 5. Forthis to occur, the erase can be accomplished by applying approximately10 volts to the substrate while the word line is set at approximatelyzero volts.

[0035] Although representative voltages and timing patterns have beendescribed for writing, reading and erasing a memory cell of theinvention, these are merely exemplary. Many changes and modificationscan be made to produce, write, read and erase signals which areequivalent to those described above and which can be used in anequivalent manner to operate the memory cell transistor 1 in the write,read and erase modes.

[0036] The manner of fabricating transistor 1 having floating gates 3and 5 will now be described with reference to FIGS. 7-24. A firstfabrication embodiment is described with reference FIGS. 7-18, while asecond fabrication embodiment is described with respect to FIGS. 19-24.

[0037]FIG. 7 illustrates a P-channel silicon substrate 101 which has afield oxide region 102 which surrounds isolates and defines the boundaryof an active area (e.g. area 17 in FIG. 3) in which transistor 1 will befabricated. FIG. 7 also illustrates that an oxide layer 103 e.g. silicondioxide, has been applied and on top of that, a first polysilicon layer105 has been deposited. Over this, another deposited layer in the formof silicon nitride is applied. It should be understood that thoseskilled in the art readily understand the deposition, masking andetching steps needed to construct the structure illustrated in FIG. 7.

[0038]FIG. 8 illustrates subsequent processing steps. In FIG. 8 anadditional oxide layer 109, e.g. silicon dioxide, is applied over theentire surface of the silicon substrate 101. The oxide layer 109 overthe nitride layer 107 is removed by an RIE etch to form oxide spacers113, 115. The RIE etch of the oxide layer 109 leaves oxide spacerregions 113 and 115 on either side of the polysilicon region 105 andsilicon nitride layer 107. Afterwards, as shown in FIG. 9 anotherpolysilicon layer 111 is applied over the entire surface of thesubstrate 101. The polysilicon layer 111 is then partially removed byplanarization to produce the structure illustrated in FIG. 10. As shown,the nitride layer 107 is somewhat reduced in thickness, but thepolysilicon layer 105 is still intact, as are the spacer regions 113 and115.

[0039] Following this, as illustrated in FIG. 11, a photoresist 117 isapplied for the purposes of etching the remaining polysilicon layer 111.The photoresist layer 117 as well as the nitride layer 107 and oxidespacer 115 serve as a mask for the etching process so that, as shown inFIG. 12, once etched, the polysilicon layer 111 remains only in theregion to the right of spacer 113 and below the photoresist layer 117.The width “W₁” of area 111 may be larger than or smaller than the width“W₂” of area 105 in the direction of the length of the transistorbetween the field oxide region 102, as shown in FIG. 12. In the nextstep the oxide spacer 115 and remaining portion of oxide layer 109 areremoved, as illustrated in FIG. 13, by etching. In the next step, thephotoresist layer 117 is removed as is the nitride layer 107 which waspresent over the polysilicon layer 105, leaving the structureillustrated in FIG. 14. FIG. 14 now shows two adjacent polysiliconlayers, 105 and 111, separated by an oxide spacer 113. These will becomethe floating gate regions 3 and 5 of transistor 1.

[0040]FIG. 15 illustrates the structure of FIG. 14 after an ONO (oxide,nitride, oxide) layer is applied over the substrate. Following this, asshown in FIG. 16, a polysilicon word line 121 is deposited which alsoserves as the control gate for the transistor 1. The width “W₃” of wordline 121 is less than or equal to the width “W₄” of the combinedstructure formed by layers 105, 111, 113 and 119. Following this, asshown in FIG. 17, a polysilicide layer 131, is applied, which alsoserves as a mask to remove the ONO layer 119 from those portions of thesubstrate not covered by the polysilicide layer 131. Although FIG. 17shows polysilicide layer 131 over layer 121 extending as wide as thepolysilicon floating gate layers 105, 111, in practice the polysilicidelayer 131 over layer 121 may not extend over the full width of thepolysilicon floating gate regions 105, 111.

[0041] Subsequent to removal of the exposed ONO layer 119, a diffusionprocess is employed to diffuse N+regions into the substrate which willform the source 8 and drain of the transistor 1. Then, the entiresurface of the substrate is covered with a BPSG layer 133. This layer isthen subjected to a high temperature process to activate the dopant inthe channels and to cause the BPSG to soften and flow into smallcrevices in the integrated circuit. A plug 135 is then etched in theBPSG layer 133 down to the surface of the substrate 101 above sourceregion 8, as shown in FIG. 18. FIG. 18 also shows in dotted line form anadditional plug formed over drain region 10 at a differentcross-sectional location in the substrate. See, for example, FIG. 3showing the source 8 and drain 10 regions. FIG. 17 also illustrates plug135 as containing a conductive wall 137 which extends from a conductivelayer 139 applied only the BPSG layer 133 down to source region 8. Theconducting layer 139 serves as digit line 25 connecting to the sourceregion 8 through the conductive side wall 137 of the plug 135. Likewise,the other digit line 27, not shown in FIG. 18, connects through thedotted line plug in FIG. 18 to the drain region 10. The conductive layer139 may be formed as a Ti liner which is covered by a Ti N barrier withthe plug 135 then being filled with a WSix fill.

[0042] Subsequently, conventional processing steps are applied to theintegrated circuit of FIG. 18 to form the metal interconnect patternsusing resist, alloying, and finally passivation layers and bond padpattern etching to complete the integrated circuit die.

[0043] An alternate method for forming transistor 1 with the twofloating gates is illustrated in FIGS. 19-24. FIG. 19 illustrates theP-type substrate 101 having the field oxide 102 deposited therein forisolating active area 17 (FIG. 3). Subsequently, a pair of spaced apartpolysilicon channels 141 and 143 are deposited on the oxide layer 102.These channels will form the floating gate regions 3 and 5. An ONOinsulating layer 119 is then formed over the entire substrate surface asillustrated in FIG. 21. The ONO layer is selectively removed from thesubstrate except for the areas over and between the floating gateregions 141 and 143. Polysilicon word line 105 is then formed over thefloating gate regions 141 and 143. The word line 105 includes an area151 which extends down and into the space separating the two polysiliconfloating gate regions 141 and 143. A polysilicide layer 145 is alsoprovided on top of the word line polysilicon layer 105.

[0044] The polysilicide layer 145 is used as the mask for diffusion ofthe N+source and drain regions 8 and 10 in substrate 101, as shown inFIG. 23. A BPSG layer 133 is then applied as in the previous embodiment.The pattern contact layer 139, plug 135, and conductive sidewall 137, asillustrated in FIG. 24, are all formed as described above with respectto FIG. 18.

[0045] The subsequent stages of processing the integrated circuit toform the interconnects, bonding pads etc., are as described above withrespect to the first fabrication embodiment.

[0046]FIG. 25 illustrates use of a flash memory containing the inventionas the read only memory device 205 in a computer system which includes amicroprocessor 201, a RAM memory 203, bus structure 207 and severalinput/output devices 209.

[0047] Although the multi-bit decoding of each cell transistor 1 isaccomplished by separately reading -the charges from each floating gateby the current flow from one transistor region to another and thesubsequent decoding the two read out values, it is also possible todetermine the threshold voltage Vt, which is set by the combination ofcharges on the two floating gates, directly. This is illustrated in FIG.26. The source 10 of a selected transistor 1 is connected to a firstvoltage e.g. approximately 5 V, and the drain to a second voltage, e.g.ground, and a digitally controlled ramp voltage from generator 301 isconnected to word line 19 (control gate) for the transistor. As the gateramp voltage increases based on the digital value input to generator 301the transistor 1 will turn on at a ramp voltage level corresponding tothe threshold voltage Vt of the cell, which in turn is determined by thecharges stored on the floating gates. The ramp voltage at the time thetransistor turns on by the digital input to generator 301 corresponds toVt. Accordingly, when the transistor 1 turns on an associated senseamplifier 305 operates a gate 303 to pass the digital input to generator301, representing the ramp output voltage, to decoder 307 which decodesthe digital data to produce a multi-bit pattern e.g. 00, 01, 10, 11representing the data stored in the cell.

[0048] In addition, although each of the floating gate regions 3,5stores a charge which varies between two levels, it is also possible tostore multiple levels of charge, e.g. 3 or more levels in each floatinggate, which are read out, with the multi-level charges from each of thetwo floating gates being fed into a decoder for determining a multi-bitbinary value stored in each transistor 1. If three levels of charge arestored for each floating gate, a total of 9 possible combinations ofcharge could be stored in each memory cell enabling storage of a 3 bitbinary value in each cell. Storing 4 levels of charge in each floatinggate would enable each cell to store a 4-bit binary value.

[0049] Although the invention has been described with reference toparticular embodiments thereof, it should be appreciated that manychanges and modification can be made without departing from the spiritor scope of the invention. Accordingly, the invention is not to beconsidered as limited by the foregoing description, but is only limitedby the scope of the appended claims.

What is claimed is:
 1. A memory cell comprising: a word line; first andsecond digit lines; and, a transistor comprising a control gate regionconnected to said word line, source and drain regions respectivelyconnected to said first and second digit lines, and at least first andsecond floating gate regions located beneath said control gate region.2. A memory cell as in claim 1 wherein said memory cell is formed in anintegrated circuit and said at least first and second floating gateregions are located adjacent each other and separated by an insulator.3. A memory cell as in claim 2 wherein said at least first and secondfloating gate regions are located between said source and drain regions.4. A memory cell as in claim 1 wherein each of said floating gateregions are arranged to store respective charges enabling said memorycell to store a multi-bit digital value.
 5. A memory cell as in claim 4wherein said multi-bit digital value represents two bits of digitalinformation.
 6. A memory cell as in claim 4 wherein said multi-bitdigital value represents more than two bits of digital information.
 7. Amemory cell as in claim 4 further comprising an electronic circuitconnected to said word line and first and second digit lines foroperating said transistor to write and read said multi-bit digit valueto and from said memory cell.
 8. A memory cell as in claim 7 whereinsaid transistor stores at least two separate binary digit values by thecharges stored in said first and second floating gate regions.
 9. Amemory cell as in claim 7 wherein said electronic circuit applies afirst voltage to said word line and, for at least a portion of theduration of the application of said first voltage to said word line, asecond voltage to a digit line connected with one of said first andsecond floating gate regions to store a charge in said one floating gateregion.
 10. A memory cell as in claim 9 wherein said electronic circuitfurther applies a third voltage to a digit line associated with theother of said first and second floating gate regions for at least aportion of the duration of the application of said first voltage tostore a charge in said other floating gate region.
 11. A memory cell asin claim 4 wherein a gate region threshold voltage Vt of said transistoris related to the value of the charges stored in said first and secondfloating gate regions.
 12. A memory cell as in claim 10 wherein saidelectronic circuit applies said second and third voltages in sequencefor at least a portion of the duration that said electronic circuitapplies said first voltage to said word line.
 13. A memory cell as inclaim 7 wherein said electronic circuit applies a fourth voltage to saidword line, and for at least a portion of the duration of the applicationof said fourth voltage to said word line, a fifth voltage to a digitline associated with one of said first and second floating gate regionsto read a bit value defining charge stored in said one floating gateregion.
 14. A memory cell as in claim 13 wherein said electronic circuitapplies a sixth voltage to a digit line associated with the other ofsaid first and second floating gate regions for at least a portion ofthe duration of the application of said fourth voltage to said word lineto read a bit value defining charge stored in said other floating gateregion.
 15. A memory cell as in claim 14 wherein said electronic circuitapplies said fifth and sixth voltages in sequence for at least a portionof the duration that said electronic circuit applies said fourth voltageto said word line.
 16. A memory cell as in claim 1 wherein said memorycell is part of a flash memory array.
 17. A memory cell as in claim 14further comprising a decoder responsive to the charges read from saidfirst and second floating gate regions for providing a multi-bit binaryvalue representing the charges stored in said first and second floatinggate regions.
 18. A memory cell as shown in claim 7, wherein a gateregion turn on threshold voltage Vt of said transistor is related to thevalue of the charges stored in said first and second floating gates andwherein said electronic circuit supplies voltage to said row and firstand second digit lines in a manner which enables said threshold voltageVt to be determined.
 19. A memory cell as in claim 18 further comprisinga decoder for providing a multi-bit value in response to a determinedthreshold voltage Vt.
 20. A memory cell as in claim 18 wherein saidelectronic circuit supplies a ramp voltage to said word line whilebiasing said source and drain regions through said digit lines in amanner which causes said transistor to turn on when said ramp voltagereaches said gate region threshold voltage Vt, a representation of saidramp voltage at the time of turn on of said transistor being decoded tothereby read a multi-bit digit value from said memory cell.
 21. A methodof forming a memory cell comprising the steps of: forming a firstfloating gate region on a silicon substrate; forming a second floatinggate region on said silicon substrate; said second floating gate regionbeing adjacent to and electrically isolated from said first floatinggate region; forming an insulating layer over said first and secondfloating gate regions; forming a control gate region over saidinsulating layer and over said first and second floating gate regions;forming source and drain regions in said substrate such that said firstand second floating gate regions are located at least in part betweensaid source and drain regions; and forming electrical interconnects withsaid source, drain and control gate regions.
 22. A method as in claim 21wherein said electrical interconnects include a first digit lineconnected with one of said source and drain regions, a second digit lineconnected to the other of said source and drain regions, and a row lineconnected to said control gate region.
 23. A method as in claim 21further comprising the step of placing an insulating region between saidfirst and second floating gate regions, said first and second floatinggate regions being adjacent each other but separated by said insulatingregion.
 24. A method as in claim 21 wherein said first and secondfloating gate regions are spaced from one another, said method furthercomprising the steps of providing an insulating layer on the tops andthe side edges of said first and second floating gate regions which faceone another, and wherein said gate control region is additionally formedbetween the side edges of said first and second floating gate regionswhich face one another.
 25. A method as in claim 21 further comprisingthe steps of forming a field oxide isolating region around said memorycell to isolate said memory cell from adjacent memory cells in saidsubstrate.
 26. A method as in claim 21 further comprising the steps offorming an array of said memory cells on said silicon substrate.
 27. Amethod as in claim 21 wherein said memory cell is a memory cell of aflash memory array.
 28. A computer system comprising: a processor and aflash memory connected to said processor for storing information used bysaid processor, said flash memory comprising a plurality of arrayedmemory cells, at least some of said arrayed memory cells comprising: aword line; first and second digit lines; and, a transistor comprising acontrol gate region connected to said word line, source and drainregions respectively connected to said first and second digit lines, andat least first and second floating gate regions located beneath saidcontrol gate region.
 29. A computer system as in claim 28 wherein saidtransistor is formed in an integrated circuit and said at least firstand second floating gate regions are located adjacent each otherseparated by an insulator.
 30. A computer system as in claim 28 whereinsaid at least first and second floating gate regions are located betweensaid source and drain regions.
 31. A computer system as in claim 28wherein each of said floating gate regions is arranged to store aseparate charge enabling said transistor to store a multi-bit digitalvalue.
 32. A computer system as in claim 31 wherein said multi-bitdigital value represents two bits of digital information.
 33. A computersystem as in claim 31 wherein said multi-bit digital value representsmore than two bits of digital information.
 34. A computer system as inclaim 31 further comprising an electronic circuit connected to said wordline and first and second digit lines for operating said transistor towrite and read said multi-bit digit value to and from said memory cell.35. A computer system as in claim 31 wherein said electronic circuitapplies a first voltage to said word line and, for at least a portion ofthe duration of the application of said first voltage to said word line,a second voltage to a digit line connected with one of said first andsecond floating gate regions to store a bit value defining charge insaid one floating gate region.
 36. A computer system as in claim 35wherein said electronic circuit further applies a third voltage to adigit line associated with the other of said first and second floatinggates for at least a portion of the duration of the application of saidfirst voltage to said word line to store a bit value defining charge insaid other floating gate region.
 37. A computer system as in claim 31wherein a gate region threshold voltage Vt of said transistor is relatedto the value of the charges stored in said first and second floatinggate regions.
 38. A computer system as in claim 36 wherein saidelectronic circuit applies said second and third voltages in sequencefor at least a portion of the duration that said first electroniccircuit applies said first voltage to said word line.
 39. A computersystem as in claim 31 wherein said electronic circuit applies a fourthvoltage to said word line and for at least a portion of the duration ofthe application of said fourth voltage to said word line, a fifthvoltage to a digit line associated with one of said first and secondfloating gate regions to read a bit value defining charge stored in saidone floating gate region.
 40. A computer system as in claim 39 whereinsaid electronic circuit applies a sixth voltage to a digit lineassociated with the other of said first and second floating gate regionsfor at least a portion of the duration of the application of said fourthvoltage to said word line to read a bit value defining charge stored insaid other floating gate.
 41. A computer system as in claim 31 whereinsaid electronic circuit applies said fifth and sixth voltages for atleast a portion of the duration that said electronic circuit appliessaid fourth voltage to said word line.
 42. A computer system as in claim28 wherein said memory cell is part of a flash memory array.
 43. Acomputer system as in claim 40 further comprising a decoder responsiveto the charges read from said first and second floating gate regions forproviding a multi-bit binary value representing the charges stored insaid first and second floating gate regions.
 44. A computer system as inclaim 34 wherein a gate region turn on threshold voltage Vt of saidtransistor is related to the value of the charges stored in said firstand second floating gates and wherein said electronic circuit suppliesvoltage to said row and first and second digit lines in a manner whichenables said threshold voltage Vt to be determined.
 45. A computersystem as in claim 44, further comprising a decoder for providing amulti-bit value in response to a determined threshold voltage Vt.
 46. Acomputer system as in claim 44 wherein said electronic circuit suppliesa ramp voltage to said word line while biasing said source and drainregions through said digit lines in a manner which causes saidtransistor to turn on when said ramp voltage reaches said gate thresholdvoltage Vt, a representation of said ramp voltage at the time of turn onof said transistors being decoded to thereby read a multi-bit digitvalue from said memory cell.
 47. A method of operating a memory cellcomprising a first and second floating gate regions, a control gateregion, source and drain regions, a word line connected to said controlgate region, and first and second digit lines respectively connected tosaid source and drain regions, to store a multi-bit binary value in saidmemory cell, said method comprising the steps of: (a) controlling theselective storage of charges in said first and second floating gateregions to store a multi-bit binary value in said memory cell; and (b)selectively reading the charges stored in said first and second floatinggates region and using the read charges to determine a multi-bit binaryvalue stored in said memory cell.
 48. A method as in claim 47 whereinsaid controlling step, when storing a charge in a selected floating gateregion, comprises the step of selectively applying a voltagedifferential to said word line a digit line associated with saidselected floating gate region.
 49. A method as in claim 47 wherein saidmulti-digit binary value represents two binary bits which can be storedin said memory cell.
 50. A method as in claim 47 wherein saidmulti-digit binary value represents more than two binary bits which canbe stored in said memory cell.
 51. A method as in claim 48 wherein whencharges are to be selectively stored in each of said first and secondfloating gate regions said controlling step comprises the steps of (a)applying voltages to said word line and said first digit line toestablish a voltage differential between them to store a first charge inone of said floating gates; (b) applying a voltage to said word line andsecond digit line to establish a voltage differential between them whichstores a second charge in the other of said floating gates.
 52. A methodas in claim 51 wherein steps (a) and (b) are carried out in sequence.53. A method as in claim 47 wherein the step of reading the chargesstored in said first and second floating gate regions comprises thesteps of: applying voltage to said word line and said first digit lineto establish a voltage differential which causes a read out of a storedcharge in one of said floating gate regions; applying voltage to saidword line and said second digit line to establish a voltage differentialwhich causes a read out of a stored charge in the other floating gateregion; and decoding the read changes from said fist and second floatinggates to determine the multi-digit binary value stored in said memorycell.
 54. A method as in claim 48 wherein to store a charge in afloating gate region, a first voltage is applied to said row line and asecond voltage is applied to a digit line, said first voltage beinglarger than said second voltage.
 55. A method as in claim 47 wherein toread a charge from a selected floating gate region a third voltage isapplied to said word line, and a fourth voltage is applied to a digitline, associated with said selected floating gate region said thirdvoltage being larger than said fourth voltage.
 56. A method as in claim47 further comprising the step of erasing a multi-digit binary valuefrom said memory cell.
 57. A method as in claim 56 wherein the step oferasing comprises the steps of applying a fifth voltage to said wordline and a sixth voltage to said first and second digit lines, saidfifth and sixth voltages establishing a voltage differential across saidfirst and second floating gate regions which causes the charges on saidfloating gate regions to tunnel to said first and second digit lines.58. A method as in claim 56 wherein the step of erasing comprisesapplying a seventh voltage to said word line and an eighth voltage tosaid substrate to establish a voltage differential across said first andsecond floating gate regions which causes the charges on said floatinggate regions to tunnel to said substrate.
 59. A method as in claim 47wherein the step of sending the charges stored in said first and secondfloating gate regions comprises the steps of: supplying voltages to saidrow and first and second digit lines in a manner which enables athreshold voltage Vt of said transistor to be determined.
 60. A methodas in claim 59 further comprising the step of decoding a determinedthreshold voltage Vt value to provide a multi-bit value.
 61. A method asin claim 59 further comprising the step of providing an increase ramvoltage to said word line while biasing said transistors in a mannerwhich turns it on when said threshold voltage Vt is reached anddetermining the ramp voltage Which causes said transistor to turn on.